A digital integrated chip typically generates an internal clock used to control latches and flip-flops generated by driving a phase locked loop (PLL) with an external reference clock signal. The internal clock signal can then be adjusted in integer multiples of the reference clock signal by changing the PLL ratio. The PLL output frequency for each unique ratio for a given reference clock signal can be referred to as a “clock bin” where the number of clock bins is physically limited to the lock range of the PLL. The PLL output frequency can also be adjusted linearly by varying the external reference clock signal; however, this is generally used to reach frequencies between clock bins because the reference frequency is limited to the lock range of the PLL. The lock range of certain low-noise PLLs are extremely limited so this method has limited usage.
Designs with multiple clock and/or power domains typically employ a separate PLL for each domain fed by a single master reference clock signal. This creates dependencies that limit fine-tuning between clock bins for each domain, but a single master reference clock signal reduces cost and simplifies inter-domain signal transfer. Transferring signals between clock domains requires synchronization in order to insure determinism and avoid meta-stability. Alignment of clocks derived from the same reference can be used for synchronization, but transfer delay between domains can be slower than either domain because alignment first occurs at the least common multiple of the frequencies.
To generate clock bins that are not integer multiples of the external reference clock, the output of a phase locked loop (PLL) can be divided then used as the reference clock for another PLL. For example, an external reference clock of 100 MHz can generate a 400 MHz PLL output. This PLL output can then be divided by 3 to derive a 133 MHz reference to a secondary PLL, which provides 133 MHz clock bins such as 1866 MHz, with a PLL ratio of 14.